This invention relates to complementary metal oxide semiconductor (CMOS) devices and, more particularly, to CMOS device architectures and processes for manufacturing low voltage, high voltage, or both low voltage and high voltage CMOS devices with a reduced number of processing steps.
Typically, CMOS manufacturing processes require more processing steps than manufacturing processes for standard n-channel metal oxide semiconductor (NMOS) devices. The advantage of reduced power consumption for the CMOS devices compared to NMOS devices is offset by increased manufacturing complexity, i.e., an increased number of manufacturing process steps. The complexity of conventional CMOS manufacturing processes is further increased when both low voltage and high voltage CMOS devices are within the same circuit.
Referring to FIG. 1, a typical low-voltage CMOS device 10 consists of an n-channel (NMOS) portion 12 and a p-channel (PMOS) portion 14 formed on a p-doped substrate 18 (The term substrate, as used herein, refers to one or more semiconductor layers or structures that include active or operable portions of semiconductor devices.) The process steps required to fabricate this device are well-known to those having ordinary skill in the art. For example, one of the first steps in a CMOS fabrication process is to implant and drive in n-well 16 into p-substrate 18. A subsequent step is to mask and implant p-channel stops 20 into substrate 18. Thereafter, thick field oxide 22 is grown over p-channel stops 20, and thin gate oxide 24, 26 is grown over the surface of substrate 18. Polysilicon layer 32, 34 is added atop the thin gate oxide 24, 26, respectively, to to form gate structures of the NMOS 12 and PMOS 14 devices, respectively. Finally, in separate mask and implant steps, source/drain (S/D) regions 28 and 30 of the NMOS device 12 and PMOS device 14, respectively, are formed.
The foregoing list of CMOS fabrication steps is not intended to be comprehensive. It is well understood by those having ordinary skill in the art that additional steps are required to fabricate device 10, such as adjusting the threshold voltage (Vt) of the device through doping implantation and forming electrical contacts to substrate 18, n-well 16, S/D regions 28, 30 and gates 32, 34. Moreover, there are many equivalent and suitable known processes for forming such devices. The foregoing steps merely serve to illustrate that typical low-voltage CMOS fabrication requires two separate mask and implant steps to form p-channel stops and S/D regions for p-channel (i.e. PMOS) devices.
CMOS fabrication is further complicated by the combination of high-voltage and low-voltage CMOS devices in a single substrate. Specifically, adding a high-voltage CMOS device to low-voltage CMOS device 10 typically requires yet another set of mask and implant steps. Accordingly, a circuit bearing low and high voltage CMOS devices typically requires three separate sets of mask and implant steps to form p-channel stops, low-voltage PMOS S/D regions and high-voltage PMOS S/D regions.
As a general rule, each mask step increases the complexity of the fabrication process and reduces yield due to the increased potential for processing defects. Increased complexity has a particularly detrimental effect on process yield in high density circuit arrays. Accordingly, it is desirable to eliminate process steps in general, and mask steps in particular, from the steps necessary to fabricate both low and high voltage CMOS devices.
The present invention provides a process that eliminates certain mask and implant steps typically used to form both low- and high-voltage CMOS devices. In accordance with the present invention, semiconductor-fabrication is made more efficient by implanting one or more stop(s) and a S/D region of one or more devices in a single step. The process may be used to produce low-voltage CMOS devices, high-voltage CMOS devices or both low- and high-voltage CMOS devices on the same substrate utilizing the same fabrication sequence. This invention may contribute to lower fabrication costs through the elimination of process steps and higher overall process yield through reduced device complexity.
In one embodiment, a process for fabricating a CMOS device includes the steps of growing a thick field oxide over a substrate and selectively implanting the substrate (through the thick field oxide) to form a stop region and a source/drain region in a single process step.
In another embodiment, a process for fabricating a semiconductor device includes the steps of growing a thick field oxide over a substrate; selectively implanting the substrate through the thick field oxide to form a plurality of stop regions, a first source/drain region and a second source/drain region in a first single process step; forming a first polysilicon gate over the first source/drain region; forming a second polysilicon gate over the second source/ drain region; and doping the first and said second gates in a second single process step.
In yet another embodiment, a process for fabricating a semiconductor device includes the steps of forming a well of a first dopant type in a substrate, and selectively implanting the substrate and the well to form a stop region in the substrate and a first source/drain region in the well in a single process step, the stop region and the first source/drain region being of a second dopant type.
In another embodiment, a semiconductor device includes a stop region disposed in a substrate containing a first dopant type; a well disposed in the substrate implanted with a second dopant type; a first source/drain region disposed in the well, the first source/drain region containing the first dopant type; a thick field oxide disposed over the well; and a first gate structure disposed over the thick field oxide.
A further understanding of the nature and advantages of the invention may be realized by reference to the remaining portions of the specification and drawings.